1. Field
Various embodiments of the present invention relate to a flash memory system and, more particularly, to an operating method of flash memory system for performing error correction with a concatenated Bose-Chadhuri-Hocquenghem (BCH) code.
2. Description of the Related Art
With the increase in speed of processors and main storage devices, such as RAM, a bottleneck has occurred in various electronic devices. The bottleneck is due to processors and main storage devices being limited by the operating speed of the auxiliary storage devices. Devices that store data using magnetic fields, such as hard disk drives (HDD), and optic disc drives (ODD), such as CDs and DVDs, have generally been used for auxiliary storage devices. The speed at which optical disc devices can operate is limited, and often slow relative to processor and main memory speeds. Devices that store data using magnetic fields generally operate at higher speeds than optical disc devices, but still cause bottlenecking, and are prone to damage from physical impacts. Accordingly, solid state drives (SSD) formed using semiconductor elements may be a solution to alleviate the bottlenecking problem. Solid state drives (SSD) have processing speeds higher than HDDs, and may input and output data at high speed without requiring time to search for data that needs to be randomly accessed. In addition, since SSDs have no moving parts, there are no mechanical delays or mechanical failures and the likelihood of damage from physical impact is significantly reduced. Further, SSDs are energy efficient, do not generate a lot of heat, and are quiet. Additionally, SSDs have a small form factor and relative to HDDs, making them ideal for portable electronic devices.
In SSDs, generally NOR flash memory or NAND flash memory is used. NAND flash memory is capable of being highly integrated and has serial connections, making it suitable for high capacity memory devices, and has high read/writing speeds. Therefore, NAND flash memory is used for most mass capacity SSD.
However, NAND flash memory is constantly undergoing miniaturization as is increasing being required to store multiple bits of information per memory cell. The increased storage density results in adverse effects including decreased reliability and product life.
FIGS. 1(A) to 1(D) are a diagram illustrating distributions of threshold voltages according to a number of bits stored in a flash memory cell.
Referring to FIGS. 1(A) to 1(D), a Single-Level Cell (SLC) flash memory (FIG. 1(A)) is a NAND element that stores 1-bit information, a Multi-Level Cell (MLC) flash memory (FIG. 1(B)) is a NAND element that stores 2-bit information, a Tri-Level Cell (TLC) flash memory (FIG. 1(C)) is a NAND element that stores 3-bit information, and a Quad-Level Cell (QLC) Flash Memory (FIG. 1(D)) is a NAND element that stores 4-bit information.
Referring to FIGS. 1(A) to 1(D), the likelihood of errors caused by inter-level interference increases during reading operations when there is an increase in the number of bits stored per cell, and the error occurrence drastically increases as reading/writing operations are repeated, resulting in decreased reliability of the product overall. Therefore, an error correction circuit that is both energy efficient and has high processing power is an essential element in designing stable NAND flash memories at reasonable prices.
To resolve this concern, error correction encoding is generally used. Error correction encoding requires extra bits of data storage to store information for error detection and correction. This requires chip area for extra memory cells to store the extra bits. However, to maximize the storage capacity of the storage medium, the area used to store the extra bits is miniaturized, and the amount extra bits required needs to be minimized as well.
In addition, due to the increase of data storage errors, advanced error correction encoding has been substituted for conventional BCH encoding and Reed-Solomon (RS) encoding. This advanced error correction encoding requires exponentially greater complexity and greater data storage.
A block-wise concatenated BCH (BC-BCH) code, as a substitution for conventional BCH code and the RS code, has excellent error correction performance with hard decision information, and the BC-BCH code decoder is less complex and more easily implemented than conventional BCH code decoders. However, soft decision information is indispensable for improving the decoding performance of BC-BCH code. To this end, information similar to soft decision information needs to be generated by raising the quantization level of the hard decision information. One option is to re-read the pages where errors occur by changing the threshold voltage of the page. However, it is not efficient to re-read pages by changing the threshold voltage because it is complex and the decoding is delayed.
Therefore, when threshold voltage is read limitedly, an optimal reference voltage for minimizing the error rate of the soft decision decoder may be sets That is, the error rate of the soft decision decoder may be lowered when the quantization level is raised through setting the optimal reference voltage.
That is, an optimal quantization method for minimizing the decoding error rate is required when the soft decision decoding (i.e., the turbo BC-BCH) is performed with additionally acquired soft decision information as the hard decision information if he BC-BCH code fails.